SRS01 

         SRS01 - Block Size / Block Count
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808204

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BCCT

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

SDMABB

RW 0x0

TBS

RW 0x0

SRS01 Fields

Bit Name Description Access Reset
31:16 BCCT 
              BCCT - Block Count For Current Transfer\n
              With this field, the number of data blocks can be defined for next transfer.\n
              This register is used when SRS03.BCE is set 1,
              and SRS15.HV4E is set to 0 or SRS15.H4VE is set to 1 and this field is different than 0,
              otherwise it will be ignored.\n
              When SRS15.HV4E==1 and this field == 0. 32-bit block count register is selected (SRS00.SAAR).\n
              The value is decremented after each block transfer. When this field is set 0, no data blocks will be transferred.\n
              During data transfer read operation may return invalid value, and write operations are ignored.\n
              [list] [*] 0000h - no block transfer [*] 0001h..FFFFh - 1..65535 block(s) transfer. [/list]
RW 0x0
15 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
14:12 SDMABB 
              SDMABB - SDMA Buffer Boundary\n
              In this field, the system address boundary can be set for SDMA engine.\n
              The SDMA transfer stops crossing the address boundary and generates the DMA Interrupt (SRS12.DMAINT).\n
              After the DMA Interrupt, when the SRS15.HV4E is 0, the software should write new SDMA System Address (SRS00.SAAR / SRS22.DMASA1) in order to resume the SDMA transaction.\n
              [list]
              [*] 0 - 4k bytes address boundary
              [*] 1 - 8k bytes address boundary
              [*] 2 - 16k bytes address boundary
              [*] 3 - 32k bytes address boundary
              [*] 4 - 64k bytes address boundary
              [*] 5 - 128k bytes address boundary
              [*] 6 - 256k bytes address boundary
              [*] 7 - 512k bytes address boundary
              [/list]
RW 0x0
11:0 TBS 
              TBS - Transfer Block Size\n
              This field defines block size for block data transfers. During data transfer, read operations may return an invalid value, and write operations are ignored.\n
              The software will not set value that exceeds the physically implemented internal FIFO buffer size.
              The buffer size is equal to 2^FIFODEPTH, where FIFODEPTH is the generic parameter of the core.\n
              The SD/MMC (memory) uses block size up to 512 bytes.\n
              The SDIO can use up to 2048 bytes.\n
              [list]
              [*] 000h - not used
              [*] 001h - 1 data byte
              [*] 002h - 2 data bytes
              [*] 003h - 3 data bytes
              [*] ...
              [*] 1FFh - 511 data bytes
              [*] 200h - 512 data bytes
              [*] ...
              [*] 800h - 2048 data bytes
              [*] others - not used.
              [/list]
              Note: It is recommended for the software to use native data block size (512B) in case of multiple data block transfer (SRS03.MSBS==1).
              Using smaller block may cause unexpected response error when flow control is activated (i.e. SDCLK is disabled) during response transfer.
RW 0x0