SRS10 

         SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up)
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____SRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808200 0x10808228

Size: 32

Offset: 0x28

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_16

RO 0x0

WORM

RW 0x0

WOIS

RW 0x0

WOIQ

RW 0x0

Reserved_13

RO 0x0

IBG

RW 0x0

RWC

RW 0x0

CREQ

RW 0x0

SBGR

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_9

RO 0x0

BVS

RW 0x0

BP

RW 0x0

CDSS

RW 0x0

CDTL

RW 0x0

EDTW

RW 0x0

DMASEL

RW 0x0

HSE

RW 0x0

DTW

RW 0x0

LEDC

RW 0x0

SRS10 Fields

Bit Name Description Access Reset
31:27 Reserved_16 
Reserved bitfield added by Magillem
 RO 0x0
26 WORM 
              WORM - Wakeup Event Enable On SD Card Removal\n
              When set to 1, enables wake-up event via Card Removal assertion in the SRS12.CR register.
RW 0x0
25 WOIS 
              WOIS - Wake-Up Event Enable On Card Inserted\n
              When set to 1, enables wake-up event via Card Insertion assertion in the SRS12.CIN register.
RW 0x0
24 WOIQ 
              WOIQ - Wakeup Event Enable On Card Interrupt\n
              When set to 1, enables wake-up event via Card Interrupt assertion in the SRS12.CINT
RW 0x0
23:20 Reserved_13 
Reserved bitfield added by Magillem
 RO 0x0
19 IBG 
              IBG - Interrupt At Block Gap\n
              When set to 1, enables interrupt detection at the block gap for a multiple block transfer.\n
              This bit is valid only in SD4 mode.\n
              If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0.\n
RW 0x0
18 RWC 
              RWC - Read-Wait Control\n
              When set to 1, enables Read Wait control. The Read Wait function is optional for SDIO cards.\n
              If the card does not support read wait, this bit would never be set to 1; otherwise, DAT line conflict may occur.
RW 0x0
17 CREQ 
              CR - Continue Request\n
              When set to 1, restarts the transfer previously stopped using the Stop At Block Gap.\n
              The software will set SRS10.SBGR (Stop At Block Gap) bit to 0 before setting the (CR) Continue Request.\n
              When SRS10.SBGR=1, then all write operations to Continue Request are ignored. Clearing SRS10.SBGR can be done before or simultaneously with writing the CR.
              Continue Request bit is cleared automatically by the host when SRS09.DLA (Dat Line Active) changes from 0 to 1, indicating the actual restart of the transfer.
RW 0x0
16 SBGR 
              SBGR - Stop At Block Gap Request\n

              When set to 1, orders the stop executing read and write transaction at the next possible block gap for non-DMA, SDMA and ADMA transfers. The software will maintain SBGR=1 until the current transfer is complete (typically by waiting for - Transfer Complete bit). After Transfer Complete event, the software will set SBGR back to 0.\n

              In case of the read transfer, the host stops after the next data block received from the card.
              This uses the Read-Wait mechanism if it is enabled by SRS10.RWC, or stops the card clock (\textit{pad_mem_webar_t}) if Read-Wait is disabled.
              \n
              In the case of the write transfer, host stops after the last block written to the data buffer. The host sends all data already written to the internal data buffer before stopping the transfer.\n

              In case of stopping non-DMA write transfer, the software will set this bit only at block gap (block unit (SD mode)).
RW 0x0
15:12 Reserved_9 
Reserved bitfield added by Magillem
 RO 0x0
11:9 BVS 
              BVS - SD Bus Voltage Select\n
              This field is used to configure VDD1 voltage level.The state of this field directly drives pad_bv port.\n
              [list]
              [*] 000b-100b - Reserved
              [*] 101b - 1.8V (typical) for embedded
              [*] 110b - 3.0V (typical)
              [*] 111b - 3.3V (typical)
              [*] others - Reserved
              [/list]
RW 0x0
8 BP 
              BP - SD Bus Power for VDD1\n
              When set to 1, the VDD1 voltage is supplied to card/device. The state of this bit directly drives \textit{pad_mem_ctrl_1} pad.\n
              Setting bit to 0 cause that host stops driving SDCLK, CMD/DAT lines. If the device is connected to the host, lines go low before disabling VDD1.\n
              The host will set this bit automatically to 0 when card is removed from the slot (i.e. after high to low transition on pad_mem_ctrl_0 pin).
              This is to provide the hot removal support.
RW 0x0
7 CDSS 
              CDSS - Card Detect Signal Selection\n
              A card detection mechanism will base on either pad_mem_ctrl_0 port or register value.\n
              0 - pad_mem_ctrl_0 pin (normal mode)\n
              1 - CDTL(SRS10.6) bit (testing mode)
RW 0x0
6 CDTL 
              CDTL - Card Detect Test Level\n
              Designates card insertion status when SRS10.CDSS=1. Bit provided for test purposes.\n
              0 - no card\n
              1 - card inserted
RW 0x0
5 EDTW 
              EDTW - Extended Data Transfer Width\n
              This bit is to enable/disable 8-bit DAT bus width mode.\n
              0 - bus width selected by SRS10.DTW\n
              1 - 8-bit mode enabled
RW 0x0
4:3 DMASEL 
              DMASEL - DMA Select\n
              In this field the DMA mode can be selected. The field behaviour depends on the Host Controller Compatibility bit (SRS15.HV4E).\n
              Host Controller version 3.00 compatible mode (SRS15.HV4E=0)\n
              00b - SDMA mode\n
              01b - Reserved\n
              10b - ADMA2 (32-bit Address)\n
              11b - ADMA2 (64-bit Address)\n

              Host Controller version 4.00 compatibility mode (SRS15.HV4E=1)\n
              00b - SDMA mode\n
              01b - Not Used\n
              10b - ADMA2 mode (ADMA3 is not supported or disabled)\n
              11b - ADMA2 or ADMA3 is selected\n
              The ADMA2 address bus width is configured by 64-bit Addressing bit in Host Controller 2 register when SRS15.HV4E=1.
RW 0x0
2 HSE 
              HSE - High Speed Enable\n
              Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1).\n
              The maximum SD clock frequency is defined as 0-25MHz in the default speed mode, and 0-50MHz in the High Speed mode.
RW 0x0
1 DTW 
              DTW - Data Transfer Width\n
              Bit used to configure DAT bus width to 1 or 4.\n
              0 - 1-bit mode\n
              1 - 4-bit mode\n
              This bit is ignored when the SRS10.EDTW is set 1 (8-bit mode selected).
RW 0x0
0 LEDC 
              LEDC - LED Control\n
              State of this bit directly drives led port of the host in order to control the external LED diode.\n
              LEDC=1 will switch LED on, while LEDC=0 will switch it off.\n
              The software will switch LED on to caution the user not to remove the card while the transfer is in progress.
RW 0x0