GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.4.1. Testing in Hardware - Parallel or Serial Loopback

You can test the SDI II Design Example in hardware with parallel or serial loopback.
Table 4.  Hardware Design Example Support
Design Video Standard
HD 3G 12G
Parallel loopback with external VCXO Merging - - -
Non-Merging Yes Yes Yes
Parallel loopback without external VCXO Merging - - -
Non-Merging - - -
Serial loopback Merging Yes - -
Non-Merging Yes Yes Yes
  1. For parallel loopback:
    1. Connect an SDI video generator to the receiver input pin.
    2. Validate if RX is locked to the signal and receiving the video data correctly.
      Table 5.  User LEDs on Agilex 5 FPGA E-Series 065B Premium Development Kit
      USER SW1 LEDs  
      1 D1, D2, D3 Indicate the receiver video standard.
      1 D0 Illuminates for the slower version of TX transceiver parallel clock.
      0 D0 Illuminates for the slower version of RX transceiver parallel clock.
      0 D1 Illuminates when align_locked signal is asserted.
      0 D2 Illuminates when trs_locked signal is asserted.
      0 D3 Illuminates when frame_locked signal is asserted.
      Table 6.  D1-D3 LED Status and Video Standard on Agilex 5 FPGA E-Series 065B Premium Development Kit
      USER SW1=1 D1, D2, D3 Video standard
      000 SD
      001 HD
      010 3G Level B 10-bit multiplex
      011 3G Level A 10-bit multiplex
      100 6G 10-bit multiplex Type 2
      101 6G 10-bit multiplex Type 1
      110 12G 10-bi multiplex Type 2
      111 12G 10-bit multiplex Type 1
    3. The on-board LEDs show the RX status.
  2. For serial loopback:
    1. Connect the transmitter output pin to receiver input pin directly.
    2. Validate whether RX locks to the signal and receives the video data correctly. The on-board LEDs show the RX status.
      You may also connect an SDI signal analyzer to the transmitter output pin to view the generated image.
Level Two Title