GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 823543
Date 5/30/2025
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.1. Features

  1. To use RX- or TX-only components, remove the irrelevant blocks from the simplex version serial loopback design as described in the following table.
    Table 8.  Features
    User Requirement Preserve Remove
    RX only
    • RX top
    • Sys Reset
    • GTS Reset Sequencer
    • GTS System PLL Clock IP
    		 TX Top
    TX only
    • TX top
    • Sys Reset
    • GTS Reset Sequencer
    • GTS System PLL Clock IP
    		 RX Top
Figure 12. Components Required for TX- or RX-Only Design on Agilex™ 5 Devices
Level Two Title