GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2025.05.30 25.1 2.1.0
  • Added non-PHY simulation.
  • Added support for the Riviera simulator.
  • Added hardware support for up to 12G, including parallel loopback with external VCXO and serial loopback design.
  • Added multirate and triple-rate simulation,compilation and timing support for Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
  • Added static rate up to 12G, simulation, compilation, timing, and hardware support for Agilex™ 5 FPGA E-Series 065B Modular Development Kit.
  • Added dynamic reconfiguration option.
  • Added support for native adaption and removed the note:
    Note: The RX Adaptation mode option in the IP Analog Parameters tab is fixed to manual as SDI does not support auto adaptation.
2024.11.04 24.3 1.0.0
  • Updated Directory Structure for the Design Example figure.
  • Updated the steps to include information about Analog Parameters tab in the Generating the Design topic.
  • Updated the Design Example Tab in SDI II IP Parameter Editor figure.
  • Updated Top Level Signals table to add xcvr_rcfg_clk, user_dipsw1, user_led signals.
  • Changed fmc_vcxo_refclk_p, fmc_gbtclk1_m2c_p, and fmc_gbtclk0_m2c_p signal names to xcvr_refclk_1485, syspll_refclk, txpll_refclk respectively.
2024.09.13 24.2 1.0.0 Initial release.
Level Two Title