GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.6. Design Limitations and Known Issues

For the GTS SDI IP Design Example.

The GTS SDI II IP Design Example has the following lmitations:

  • The Agilex 5 FPGA E-Series 065B Modular Development Kit does not support dynamic reconfiguration.
  • The device package with a single quad supports only serial loopback design, because of a limitation on the number of reference transceiver clocks in the transceiver bank. For VCXO and VCXO-less designs, three reference clocks are required.
  • VCSMX and Xcelium Simulator do not support VHDL, because of limitations in the dynamic reconfiguration IP and tools.

Known Issues

Dynamic reconfiguration Critical Warning(23414): Memory depth (8192) in the design file differs from memory depth (1046) in the Memory Initialization File "xxx/support_logic/dr_top/synth/dr.mif" -- setting initial value for remaining addresses to 0

Although it's reported as a critical warning, it doesn't affect the functionalities of your design. It's safe to ignore the above problem.

GTS PMA/FEC Direct PHY IP version 5.0.0 fail to upgrade to latest Quartus Software version.

The GTS PMA/FEC Direct PHY IP version 5.0.0 generated with version 24.2 is not auto-upgrading to IP version 6.0.0 in 24.3, 24.3.1 and 25.1 because of the changes in IP parameter values.

Modification of the GTS SDI II IP Analog Parameter Settings are not reflected in the generated Design Example

Because of a problem in the Quartus Prime Pro Edition Software version 24.3, the GTS SDI II IP Analog Parameter Setting values in the generated Design Example remain at their default settings instead of reflecting any modifications made in the GTS SDI II IP GUI.

To work around this problem, make the following changes:

  1. In the generated Design Example project, open the .IP file at the Project Navigator in the "IP Components" tab:
    • For TX: ../rtl/tx/sdi_tx.ip
    • For RX: ../rtl/rx/sdi_rx.ip
  2. Update the desired Analog Parameter values in the IP Parameter Editor GUI.
  3. Save the parameter settings.
  4. Generate HDL to overwrite the .IP file.
  5. Close GUI after generating the HDL. The new values are updated.

This problem us scheduled to be fixed in Quartus Prime Pro Edition Software version 25.1.1.

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