GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.4.1. SDI II Design Example Testbench Components

Figure 23. Simplex Testbench (without Dual Simplex Generation) Block Diagram
Figure 24. Simplex Testbench (without Dual Simplex Generation and without PHY) Block Diagram
Figure 25. Simplex Testbench (with Dual Simplex Generation) Block Diagram
Table 14.  Testbench Components
Component Description
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks.
TX checker This checker verifies if the TX serial data contains a valid TRS signal.
RX checker

This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.

Parallel-in serial-out regsiter

Available when you select Without PHY in Select Simulation Type

This block acts as the TX transceiver, converting parallel TX data to serial data.
Serial-in parallel-out regsiter

Available when you select Without PHY in Select Simulation Type

This block acts as the RX transceiver, converting serial RX data to parallel data.
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