GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.4. Compiling and Testing the SDI II Design Example in Hardware

  1. Open the Quartus Prime project (sdi_ii_agi_demo.qpf) from the quartus directory.
  2. Compile the design by clicking Processing > Start Compilation.
  3. Connect the Nextera SDI daughter card to FMC port on the development kit.
  4. For parallel loopback designs, connect the BNC RX connector (J1/12G In) to an external video source and connect the TX connector (J2/12G Out) to a video analyzer.
  5. For serial loopback designs, connect the BNC TX connector (J2/12G Out) to RX connector (J1/12G In) or a video analyzer.
  6. For the Agilex 5 FPGA E-Series 065B Premium Development Kit:
    1. Toggle DIPSW SW27.4 onboard to the ON position and ensure that all other switches on the development kit are in their default positions.
      For more information, refer to the Agilex 5 FPGA E-Series 065B Premium Development Kit user guide.
    2. Open Clock Controller GUI, click the Si5332 U412 tab, and set OUT2 to 148.5 MHz
    Figure 6. Agilex 5 Premium Development Kit Clock Controller
  7. For the Agilex 5 FPGA E-Series 065B Modular Development Kit:
    1. On the SI5332 tab, set OUT6 - OUT8 to 148.5
      Figure 7. Set SI5332
    2. On the SI569 tab, set U33 to 148.5
      Figure 8. Set SI569
    3. On the MAX10 tab, click IO Control and Clock Mux tab, and set EU21 to High (default is low).
      Figure 9. Set EU21
  8. After the compilation completes, open Programmer and program the generated .sof file to the development kit.
  9. For serial loopback designs, open System Console to control the internal video pattern generator:
    1. Go to Tools > System Debugging Tools and click System Console.
    2. After the initialization, type source ../hwtest/tpg_ctrl.tcl to open the pattern generator control GUI.
    3. Select your desired video format through the GUI.
      To allow segmented frame video formats (1080sF30, 1080sF25) and interlaced video formats (1080i60, 1080i50) to be correctly differentiated in an external analyzer, insert payload ID in the serial loopback design.
      Figure 10. Selecting Video Format Through System Console
  10. The analyzer should be able to display the video generated from the source. Refer to jumper settings in the Jumper Settings and Descriptions table to change the jumper (J8) position before switching between fractional frame rate and integer frame rate video format. Press the push button (PB0) to trigger a device (LMK03328) power cycling through the PDN pin every time you change the jumper (J8) position.
    Figure 11. Jumper Settings on Nextera 12G-SDI FMC Daughtercard
    Table 3.  Jumper Settings and Descriptions
    Jumper Block Description Setting
    J7 Programming Header -
    J8

    To switch the generated clock frequency to TX channel:

    • Pin 1-2 = 297 MHz
    • Pin 2-3 = 297/1.001 MHz
    		 1-2: 297 MHz

    2-3: 297/1.001 MHz
    J9

    To select SDI or IP mode:

    • Pin 1-2 = SDI mode
    • Pin 2-3 = IP mode
    		 1-2

Section Content
Testing in Hardware - Parallel or Serial Loopback

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