GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.4.2. Test Description

The SDI II design example simulation only checks for the assertion of trs_locked signal and the number of transceiver reconfiguration triggered after every video standard switching.
Figure 26. Video Standard Sequence - Triple Rate DesignThe following figure shows the sequence of the video standard for triple-rate design:
Figure 27. Video Standard Sequence - Multirate Design

The following figure shows the sequence of the video standard for multi-rate design:

For single-rate design, the IP tests one video standard:

  • HD single-rate – HD
  • 3G single-rate – 3G Level A 10-bit Multiplex
  • 12G single rate – 12G 10-bit Multiplex Type 1

Figure 28. Simulation Waveform
Table 15.  Signals Description
Testbench signal Description
/tb_top/tb_rx_checker/rx_std Video standard keeps switching after obtaining lock signal
/tb_top/tb_rx_checker/align_locked Lock signals from IP
/tb_top/tb_rx_checker/trs_locked
/tb_top/tb_rx_checker/reconfig_count Actual number of transceiver reconfiguration triggered after every video standard switching versus the expected number of configurations.
/tb_top/tb_rx_checker/expected_rcfgcount

The following message in the simulator indicates a succesful test:

Level Two Title