GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.1. SDI II Design Example Directory Structure

The directories contain the generated files for the design example.
Figure 2. Directory Structure for the SDI II Design Example
Table 1.  Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/pfd/clock_crossing.v 0
/pfd/clock_crossing.sdc
/pfd/pfd.sdc
/pfd/pfd.v
/reclock/pid_controller.sv
/reclock /rcfg_pll_frac.sv
/reclock/sdi_reclock.sv
rx /rx_<vid_std>_top.sv 1
/sdi_rx.ip
/sdi_rx_dr_gts.sv (Only in triple- or multi-rate design examples)
/dphy_rx.ip 1
<sdi_rx ip generated folder>
<dphy_rx ip generated folder> 1
tx /tx_<vid_std>_top.sv 1
/sdi_tx.ip
/dphy_tx.ip 1
<sdi_tx ip generated folder>
<dphy_tx ip generated folder> 1
phy_adapter /sdi_phy_adapter.sv
/sdi_phy_adapter.sdc
/rxdata_dcfifo.ip
/txdata_fifo.ip
<ip generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
aldec

/aldec.do

/rivierapro_setup.tcl

/run_rivierapro_setup.tcl

common /modelsim_files.tcl
/riviera_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
mentor /mentor.do
/msim_setup.tcl
/run_msim_setup.tcl
synopsys /vcsmx/_device_sysnopsys_sim.setup
/vcsmx/synopsys_sim.setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench /tb_top.sv
/piso.sv (for simulation without PHY)
/sipo.sv (for simulation without PHY)
/rx_checker/sdi_ii_tb_rx_checker.v
/rx_checker/tb_data_compare.v
/rx_checker/tb_dual_link_sync.v
/rx_checker/tb_fifo_line_test.v
/rx_checker/tb_frame_locked_test.sv
/rx_checker/tb_ln_check.v
/rx_checker/tb_rxsample_test.v
/rx_checker/tb_trs_locked_test.sv
/rx_checker/tb_txpll_test.sv
/rx_checker/tb_vpid_check.v
/tb_control/sdi_ii_tb_control.v
/tb_control/tb_clk_rst.v
/tb_control/tb_data_delay.v
/tb_control/tb_serial_delay.sv
/tb_control/tb_tasks.v
/tx_checker/sdi_ii_tb_tx_checker.v
/tx_checker/tb_serial_check_counter.v
/tx_checker/tb_serial_descrambler.v
/tx_checker/tb_tx_clkout_check.v
/vid_pattgen/sdi_ii_colorbar_gen.v 2
/vid_pattgen/sdi_ii_ed_vid_pattgen.v 2
/vid_pattgen/sdi_ii_makeframe.v 2
/vid_pattgen/sdi_ii_patho_gen.v 2
xcelium /cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
/cds_libs
1 For Agilex™ 5 SDI_II wrapper = BASE only
2 For parallel loopback designs
Level Two Title