GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
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Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.5. SDI II Design Example Signals

Table 16.  SDI II Design Example Top-Level Signals
Signal Name Direction Width Description
On-board Oscillators
xcvr_refclk_1485 Input 1 148.5 MHz dedicated transceiver reference clock.
core_refclk_1485 Input 1 100 MHz GPIO clock.

You can change the clock frequency to 148.5 MHz in Clock Control GUI.

xcvr_rcfg_clk Input 1 Dedicated transceiver reconfiguration clock with default clock frequency of 100 MHz.
txpll_refclk Input 1 Dedicated transceiver reference clock with default clock frequency of 153.25 MHz. You can change the clock frequency in Clock Control GUI to:
  • 141 MHz in a parallel loopback without external VCXO design to connect to the TX PLL in fractional mode
User DIP Switches, Pushbuttons and LEDs
fpga_core_resetn Input 1 Global reset.
user_dipsw1 Input 1 DIP switch to switch the LEDs to display between rx_std or RX lock status.
user_led Input 4 Red LED display.
Nextera SDI FMC Daughter Card Pins on FMC
syspll_refclk Input 1 312.5 MHz dedicated system PLL reference clock from FMC.
txpll_refclk Input 1 297/296.7 MHz dedicated transceiver reference clock from FMC.
fmc_rx2_p /fmc_rx2_n Input 1 SDI RX serial data from FMC.
fmc_tx0_p /fmc_tx0_n Output 1 SDI TX serial data from FMC.
lmk03328_pdn Output 1

LMK03328 Device Power Down (active low)

fmc_lmh1983_init Output 1 LMH1983 Init
fmc_fpga_fldn Output 1

Field sync signal to LMH1983

fmc_fpga_vsyncn Output 1

V sync signal to LMH1983

fmc_fpga_hsyncn Output 1

H sync signal to LMH1983

Table 17.  RX Top and TX Top Parameters
Parameter Name Valid Value Default Value Description
NUM_STREAMS 1, 4 1 Defines the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1.
Table 18.  RX Top and TX Top Parameter SignalsThe DUTs are different if the parameter value is different. For more information about the DUT, refer to the figures in Clocking Scheme.
Note: These signals are available when SDI_II wrapper = BASE only.
Signal Name Direction Width5 Description
Clocks
system_pll_clk Input 1 System PLL output clock. This port must be connected to the system PLL output port from GTS System PLL Clocks IP.

This signal is not available when Enable Dual Simplex Generation = 1.

pma_cu_clk Input 1 Reset sequencer output clock. This port must be connected to the reset sequencer output port from GTS System PLL Clocks IP.

This signal is not available when Enable Dual Simplex Generation = 1.

rx_cdr_refclk Input 1 RX transceiver reference clock.

This signal is not available when Enable Dual Simplex Generation = 1.

rx_core_refclk Input 1 SDI RX IP clock. This clock must be a free-running clock and ranges between 100-156.25 MHz.
tx_pll_refclk Input 1 TX PLL reference clock.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_rcfg_mgmt_clk Input 1 TX reconfiguration management clock.

This signal is not available when Enable Dual Simplex Generation = 1.

sdi_tx_pclk Input 1 SDI TX IP parallel clock. This clock must be driven by one of the TX transceivers recovered parallel clocks.
rx_vid_clkout Output 1 RX transceiver recovered parallel clock for video data.
tx_vid_clkout Output 1 TX transceiver recovered parallel clock for video data.

This signal is not available when Enable Dual Simplex Generation = 1.

Reset
sdi_tx_reset Input 1 TX IP reset signal.
tx_phy_reset Input 1 TX PHY reset signal.

This signal is not available when Enable Dual Simplex Generation = 1.

rx_reset Input 1 RX IP and PHY reset signal.
sdi_rx_rst_proto_out Output 1 Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.
Video Signal Interfaces
rx_vid_data Output 20*N Receiver parallel video data out.
rx_vid_datavalid Output 1

Data valid signal generated from SDI RX IP and has the following timing synchronous to rx_vid_clkout:

SD-SDI: 1H 4L 1H 5L

HD/3G/6G/12G-SDI: H
rx_vid_std Output 3 Received video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
rx_vid_locked Output 1 Frame locked indicating multiple frames with same timing have been spotted.
rx_vid_hsync Output N Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
rx_vid_vsync Output N Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
rx_vid_f Output N Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
rx_vid_trs Output N Receiver output signal that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.
tx_vid_data Input 20*N Transmitter parallel video data input.
tx_vid_datavalid Input 1

Data valid for the transmitter parallel data. The timing (H:High, L:Low) must be as follows and synchronous to tx_pclk clock domain:

SD-SDI: 1H 4L 1H 5L

HD-SDI: 1H 1L (for triple/multi-rate)

H (for single-rate)

3G/6G/12G-SDI: H

tx_vid_std Input 3 Indicates the desired transmit video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
tx_vid_trs Input 1 Transmitter TRS input. For use in line number, CRC or payload ID insertion. Assert on first word of both EAV and SAV TRSs.
Other SDI Video Protocol Interfaces
sdi_tx_enable_crc Input 1 Enable CRC insertion for all SDI video standards except SD-SDI.
sdi_tx_enable_ln Input 1 Enable Line Number insertion for all SDI video standards except SD-SDI.
sdi_tx_ln Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1.
sdi_tx_ln_b Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit Multiplex Type 2.
sdi_tx_vpid_overwrite Input 1 Enable this signal to overwrite the existing payload ID embedded in the data stream.
sdi_tx_line_f0 Input 11*N Indicates the line number to be inserted with Payload ID.
sdi_tx_line_f1 Input 11*N
sdi_tx_vpid_byte1 Input 8*N Payload ID byte to be inserted in the payload ID field.
sdi_tx_vpid_byte2 Input 8*N
sdi_tx_vpid_byte3 Input 8*N
sdi_tx_vpid_byte4 Input 8*N
sdi_tx_vpid_byte1_b Input 8*N
sdi_tx_vpid_byte2_b Input 8*N
sdi_tx_vpid_byte3_b Input 8*N
sdi_tx_vpid_byte4_b Input 8*N
sdi_tx_datavalid Output 1 Data valid signal generated from SDI TX IP and has the following timing synchronous to tx_vid_clkout:
  • SD-SDI: 1H 4L 1H 5L
  • HD-SDI: 1H 1L (for triple/multi-rate)
  • H (for single rate)
  • 3G/6G/12G-SDI: H
sdi_rx_align_locked Output 1 Alignment locked indicating a TRS has been spotted and word alignment performed.
sdi_rx_trs_locked Output N TRS locked indicating six consecutive TRS with same timing have been spotted.
sdi_rx_clkout_is_ntsc_paln Output 1

Indicates that the receiver is receiving video rate at integer or fractional frame rate.

  • 0 – Integer frame rate
  • 1 – Fractional frame rate
sdi_rx_format Output 4*N Received video transport format. Refer to IP User Guide for the encoding value.
sdi_rx_ap Output N Active picture interval timing signal. This signal is asserted when the active picture interval is active.
sdi_rx_eav Output N Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word.
sdi_rx_ln Output 11*N Received line number output from protocol.
sdi_rx_ln_b Output 11*N
sdi_rx_crc_error_c Output N CRC error status signal from protocol.
sdi_rx_crc_error_y Output N
sdi_rx_crc_error_c_b Output N
sdi_rx_crc_error_y_b Output N
sdi_rx_line_f0 Output 11*N Payload ID status signal from protocol.
sdi_rx_line_f1 Output 11*N
sdi_rx_vpid_byte1 Output 8*N
sdi_rx_vpid_byte2 Output 8*N
sdi_rx_vpid_byte3 Output 8*N
sdi_rx_vpid_byte4 Output 8*N
sdi_rx_vpid_checksum_error Output N
sdi_rx_vpid_valid Output N
sdi_rx_vpid_byte1_b Output 8*N
sdi_rx_vpid_byte2_b Output 8*N
sdi_rx_vpid_byte3_b Output 8*N
sdi_rx_vpid_byte4_b Output 8*N
sdi_rx_vpid_checksum_error_b Output N
sdi_rx_vpid_valid_b Output N
Transceiver Interfaces
gxb_rx_serial_data Input 1 RX transceiver serial data.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_rx_serial_data_n Input 1 Differential pair of gxb_rx_serial_data.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_serial_data Output 1 TX transceiver serial data.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_serial_data_n Output 1 Differential pair of gxb_tx_serial_data.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_rx_ready Output 1 Indicates that RX transceiver is out of reset and ready for data transfer.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_ready Output 1 Indicates that TX transceiver is out of reset and ready for data transfer.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_reset_ack Output 1 Indicates that TX transceiver is reset.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_rx_reset_ack Output 1 Indicates that RX transceiver is reset.

This signal is not available when Enable Dual Simplex Generation = 1.

tx_pll_locked Output 1 TX PLL lock status.

This signal is not available when Enable Dual Simplex Generation = 1.

cdr_reconfig_busy Output 1 RX CDR reconfiguration status.
tx_reconfig_busy Output 1 TX PLL / transceiver reconfiguration status.
Transceiver Dynamic Reconfiguration Interfaces
gxb_tx_reconfig_xcvr_avmm_write 6 Output 1 Reconfiguration interface signals to Direct PHY IP's Avalon® memory-mapped interface for PLL fractional counter reconfiguration.

This signal is not available when Enable Dual Simplex Generation = 1.

gxb_tx_reconfig_xcvr_avmm_read 6 Input 1
gxb_tx_reconfig_xcvr_address 6 Input 18
gxb_tx_reconfig_xcvr_writedata 6 Input 32
gxb_tx_reconfig_xcvr_avmm_byteenable 6 Input 4
gxb_tx_reconfig_xcvr_avmm_readdata 6 Output 1
gxb_tx_reconfig_xcvr_avmm_readdatavalid 6 Output 1
gxb_tx_reconfig_xcvr_avmm_waitrequest 6 Output 1
Table 19.  Loopback Top Parameter
Parameter Name Valid Value Default Value Description
XCVR_RCFG_ADDR_WIDTH 6 18 18 Defines the reconfiguration Avalon® memory-mapped interface address bus width.
XCVR_RCFG_DATA_WIDTH 6 32 32 Defines the reconfiguration Avalon® memory-mapped interface data bus width.
FGT_LANE_NUM 6 0-3 0

Defines the lane number where the TX PLL to be reconfigured is located.

TX_PLL_MODE 6 Fast, Medium, Slow Medium

Defines the TX PLL band.

You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode.

NUM_STREAMS 1, 4 1 Defines the number of 20-bit data streams from SDI IP. For multirate mode, the value should be set to 4 while for other modes, the value should be set to 1.
VIDEO_STANDARD hd, 3g, tr, mr tr Defines the current video standard mode of SDI IP that this loopback module is interacting with.
Table 20.  Loopback Top Signals
Signal Name Direction Width 7 Description
Clocks
sdi_tx_clkout Input 1 TX transceiver recovered parallel clock for video data.
sdi_rx_clkout Input 1 RX transceiver recovered parallel clock for video data.
sdi_reclk_sysclk Input 1 Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk.
Resets
sdi_rx_rst_proto Input 1 Reset signal from RX SDI IP to indicate that the protocol is currently held in reset.
sdi_reclk_rst Input 1 Reset signal to reclock module (without external VCXO solution).
gxb_tx_ready Input 1 Used as a reset signal to internal FIFO to indicate that the TX is ready to receive.

This signal is not available when Enable Dual Simplex Generation = 1.

SDI Related Signals
sdi_rx_dataout Input 20*N Receiver recovered parallel video data.
sdi_rx_dataout_valid Input 1 Data valid signal generated from SDI RX IP.
sdi_rx_std Input 3 Received video standard from SDI RX IP.
sdi_rx_trs Input N Receiver output signal from SDI IP that indicates current word is TRS.
sdi_rx_trs_locked Input N TRS locked status signal from SDI RX IP.
sdi_rx_frame_locked Input 1 Frame locked status signal from SDI RX IP.
sdi_tx_dataout_valid Input 1 Data valid signal generated from SDI TX IP.
sdi_rx_h Input 1 Horizontal blanking interval timing signal extracted from SDI RX IP.
sdi_rx_format Input 4 Received video transport format.
sdi_rx_clkout_is_ntsc_paln Input 1 Indication from SDI RX IP that the receiver is receiving video rate at integer or fractional frame rate.
sdi_tx_datain Output 20*N Parallel video data input to SDI TX IP.
sdi_tx_datain_valid Output 1 Data valid for the transmitter parallel data to SDI TX IP.
sdi_tx_trs Output 1 Transmitter TRS input to indicate that the current word is a TRS to SDI TX IP.
sdi_tx_std Output 3 Indicates the desired transmit video standard to SDI TX IP.
TX PHY Reconfiguration Signals
pll_locked Input 1 PLL lock status signal.
pll_reconfig_readdata Input 32 Reconfiguration interface signals to fPLL AVMM interface.
pll_reconfig_readdatavalid Input 1
pll_reconfig_waitrequest Input 1
pll_reconfig_write Output 1
pll_reconfig_read Output 1
pll_reconfig_byteenable Output 4
pll_reconfig_writedata Output 32
pll_reconfig_address Output 18
Table 21.  Video Pattern Generator Parameters
Parameter Name Valid Value Default Value Description
OUTW_MULTP 1, 4 1 Defines the output ports width. Select 4 for a multirate design, otherwise select 1.
SD_BIT_WIDTH 10, 20 10 Defines the generated SD interface bit width. This value must match with the SD interface bit width parameter of SDI II TX IP in the same design.
TEST_GEN_ANC 0, 1 0 Enable to generate ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.
TEST_GEN_VPID 0, 1 0 Enable to generate payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h242.
Table 22.  Video Pattern Generator Signals
Signal Name Direction Width7 Description
clk Input 1 Clock signal. This clock must be connected to tx_vid_clkout clock signal from TX/Du top.
rst Input 1 Reset signal. This reset signal should be synchronized with tx_vid_clkout clock signal from TX/Du top.
bar_100_75n Input 1 Enable this signal to generate 100% colorbar pattern, else 75% colorbar pattern.
enable Input 1 This signal acts as a data valid signal to this module. This signal should be connected to sdi_tx_datavalid signal from TX/Du top.
patho Input 1 Enable this signal to generate pathological pattern.
blank Input 1 Enable this signal to generate black signal.
no_color Input 1 Enable this signal to generate bar with no color.
sgmt_frame Input 1 Enable this signal to generate payload ID for segmented frame video format when generating 1080i50 or 1080i60 video.
tx_std Input 3 Indicates the desired transmit video standard. This input signal must match with tx_vid_std on TX/Du top.
tx_format Input 4 Indicates the desired transmit video format.
dl_mapping Input 1 Enable this signal to generate data streams with dual-link mapping. This is only applicable for HD dual link or 3G Level B Dual link video standard.
ntsc_paln Input 1 Enable this signal to generate payload ID for fractional frame rate video format, else the module generates integer frame rate version.
dout Output 20*N Data output signal to be connected to tx_vid_data input signal on TX/Du top.
dout_valid Output 1 Data valid output signal to be connected to tx_vid_datavalid input signal on TX/Du top.
trs Output 1 TRS output signal to be connected to tx_vid_trs input signal on TX/Du top.
ln Output 11*N Line number output signal to be connected to sdi_tx_ln input signal on TX/Du top.
dout_b Output 20 Data output signal for link B (HD dual-link).
dout_valid_b Output 1 Data valid output signal for link B (HD dual-link).
trs_b Output 1 TRS output signal for link B (HD dual-link).
ln_b Output 11*N Line number output signal to be connected to sdi_tx_ln_b input signal on TX/Du top.
vpid_byte1 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte1 input signal on TX/Du top.
vpid_byte2 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte2 input signal on TX/Du top.
vpid_byte3 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte3 input signal on TX/Du top.
vpid_byte4 Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte4 input signal on TX/Du top.
vpid_byte1_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte1_b input signal on TX/Du top.
vpid_byte2_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte2_b input signal on TX/Du top.
vpid_byte3_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte3_b input signal on TX/Du top.
vpid_byte4_b Output 8*N Payload ID output signal to be connected to sdi_tx_vpid_byte4_b input signal on TX/Du top.
line_f0 Output 11*N Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f0 input signal on TX/Du top.
line_f1 Output 11*N Line number output signal to be inserted with Payload ID. This signal must be connected to sdi_tx_line_f1 input signal on TX/Du top.
Table 23.  Pattern Generator Control Module Signals
Signal Name Direction Width Description
avmm_clk_in_clk Input 1 Clock signal to AVMM interface.
tx_clkout_in_clk Input 1 Clock signal to Parallel I/O (PIO) IP. This clock must share the same clock as video pattern generator.
avmm_clk_reset_n Input 1 Reset signal to AVMM interface.
pattgen_rst_reset_in0 Input 1 Input reset signals to a reset synchronizer which synchronize the reset to tx_clkout_in_clk clock domain.
pattgen_rst_reset_in1 Input 1
pattgen_rst_reset_out Input 1 Output reset from reset synchronizer. This reset is synchronized to tx_clkout_in_clk clock domain and connected to video pattern generator’s input reset.
pattgen_ctrl_pio_out_port Output 12 Output control signal from PIO to control video pattern generator.
Table 24.  Reclock Module Parameter
Parameter Name Valid Value Default Value Description
XCVR_RCFG_ADDR_WIDTH 6 18 18 Defines the reconfiguration Avalon® memory-mapped interface address bus width.
XCVR_RCFG_DATA_WIDTH 6 32 32 Defines the reconfiguration Avalon® memory-mapped interface data bus width.
FGT_LANE_NUM 6 0-3 0

Defines the lane number where the TX PLL to be reconfigured is located.

TX_PLL_MODE 6 Fast, Medium, Slow Medium Defines the TX PLL band. You may refer to Direct PHY IP GUI to get its value when you enable TX FGT PLL fractional mode.
VIDEO_STANDARD hd, 3g, tr, mr tr

Defines the current video standard mode of SDI IP that this loopback module is interacting with.

Table 25.  Reclock Module
Signal Name Direction Width Description
Clocks
tx_clkout Input 1 TX transceiver recovered parallel clock for video data.
rx_clkout Input 1 RX transceiver recovered parallel clock for video data.
sysclk Input 1 Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk.
Resets
rx_rst_proto Input 1 Reset signal from RX SDI IP to indicate that the protocol is currently held in reset.
reset Input 1 Reset signal to reclock module (without external VCXO solution).
SDI Related Signals
rx_std Input 3 Received video standard from SDI RX IP.
rx_trs_locked Input N7 TRS locked status signal from SDI RX IP.
rx_frame_locked Input 1 Frame locked status signal from SDI RX IP.
rx_h Input 1 Horizontal blanking interval timing signal extracted from SDI RX IP.
rx_format Input 4 Received video transport format.
rx_clkout_is_nts c_paln Input 1 Indication from SDI RX IP that the receiver is receiving video rate at integer or fractional frame rate.
TX PHY Reconfiguration Signals
pll_locked Input 1 PLL lock status signal.
read_data Input 32 Reconfiguration interface signals to fPLL AVMM interface.
read_data_valid Input 1
waitrequest_signal Input 1
write_signal Output 1
read_signal Output 1
byte_enable_signal Output 4
write_data Output 32
address_signal Output 18
Table 26.  Dual Simplex Module Signals Enable Dual Simplex Generation is on and Video Standard is HD,3G or 12G
Signal Name 8 Direction Width 7 Description
rx_cdr_refclk_p_# Input 1 RX transceiver reference clock.
rx_coreclkin_# Input 1 SDI RX IP clock. This clock must be a free-running clock and ranges between 100 and 156.25 MHz.
rx_reset_# Input 1 RX PHY reset signal.
rx_serial_data_# Input 1 RX transceiver serial data.
rx_serial_data_n_# Input 1 Differential pair of rx_serial_data.
rx_clkout_# Output 1 System PLL clkout divide by 2.
rx_clkout2_# Output 1 RX transceiver recovered parallel clock for video data.
rx_is_lockedtodata_# Output 1 Indicates RX is locked to data.
rx_is_lockedtoref_# Output 1 Indicates RX is locked to reference clock.
rx_parallel_data_# Output 80 RX parallel data.
rx_ready_# Output 1 Indicates that RX transceiver is out of reset and ready for data transfer.
rx_reset_ack_# Output 1 Indicates that RX transceiver is reset.
tx_cadence_fast_clk_# Input 1 Fast clock input for tx_cadence generator. This clock should be the system clock used (or (system clock)/2 when IP Interface is double width).
tx_cadence_slow_clk_# Input 1 Slow clock input for tx_cadence generator. This clock should be the PMA word/bond clock (or (PMA word/bond clock)/2 when IP Interface is double width ).
tx_coreclkin_# Input 1 TX parallel clock input.
tx_parallel_data_# Input 80 TX parallel data.
tx_pll_refclk_p_# Input 1 SDI TX IP parallel clock. This clock must be driven by one of the TX transceivers recovered parallel clocks.
tx_reset_# Input 1 TX PHY reset signal.
tx_cadence_# Output 1 This signal indicates the rate at which tx_datavalid pin needs to be asserted or deasserted when system is running at a higher clock rate then PMA word or bond clock.
tx_clkout_# Output 1 System PLL clkout divide by 2.
tx_clkout2_# Output 1 TX transceiver recovered parallel clock for video data.
tx_pll_locked_# Output 1 TX PLL lock status.
tx_ready_# Output 1 Indicates that TX transceiver is out of reset and ready for data transfer.
tx_reset_ack_# Output 1 Indicates that TX transceiver is reset.
tx_serial_data_# Output 1 TX transceiver serial data.
tx_serial_data_n_# Output 1 Differential pair of tx_serial_data.
pma_cu_clk Input 1 PMA control unit clock output, 1 per quad of a shoreline.
src_rs_grant Input 1 Grant from GTS Reset Sequencer to SRC lane that allows SRC lane to drive or toggle a reset.
system_pll_clk Input 1 System PLL output clock. Connect this port to the system PLL output port from GTS System PLL Clocks FPGA IP.
system_pll_lock Input 1 Lock signal of System PLL.
src_rs_req Output 1 Request from SRC lane to the GTS Reset Sequencer when it wants to toggle a reset.
rx_vid_data_# 9 Output 20*N

Receiver parallel video data out.
rx_vid_datavalid_# 9 Output 1
Data valid signal generated from SDI RX IP and has the following timing synchronous to rx_vid_clkout:
  • SD-SDI: 1H 4L 1H 5L
  • HD/3G/6G/12G-SDI: H
rx_vid_std_# 9 Output 3 Received video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
rx_vid_locked_# 9 Output 1 Frame locked indicating the IP spots multiple frames with same timing.
rx_vid_hsync_# 9 Output N Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
rx_vid_vsync_# 9 Output N Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
rx_vid_f_# 9 Output N Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
rx_vid_trs_# 9 Output N Receiver output signal that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.
sdi_rx_rst_proto_out_# 9 Output 1 Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.
sdi_rx_align_locked_# 9 Output 1 Alignment locked indicating the IP spots a TRS and performs word alignment.
sdi_rx_trs_locked_# 9 Output N TRS locked indicating the IP spots six consecutive TRS with same timing.
sdi_rx_clkout_is_ntsc_paln_# 9 Output 1 Indicates that the receiver is receiving video rate at integer or fractional frame rate.
  • 0 – Integer frame rate
  • 1 – Fractional frame rate
sdi_rx_format_# 9 Output 4 Received video transport format.
sdi_rx_ap_# 9 Output N Active picture interval timing signal. This signal is asserted when the active picture interval is active.
sdi_rx_eav_# 9 Output N Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word.
sdi_rx_ln_# 9 Output 11*N Received line number output from protocol.
sdi_rx_ln_b_# 9 Output 11*N
sdi_rx_crc_error_c_# 9 Output N CRC error status signal from protocol.
sdi_rx_crc_error_y_# 9 Output N
sdi_rx_crc_error_c_b_# 9 Output N
sdi_rx_crc_error_y_b_# 9 Output N
sdi_rx_line_f0_# 9 Output 11*N Payload ID status signal from protocol.
sdi_rx_line_f1_# 9 Output 11*N
sdi_rx_vpid_byte1_# 9 Output 8*N
sdi_rx_vpid_byte2_# 9 Output 8*N
sdi_rx_vpid_byte3_# 9 Output 8*N
sdi_rx_vpid_byte4_# 9 Output 8*N
sdi_rx_vpid_checksum_error_# 9 Output N
sdi_rx_vpid_valid_# 9 Output N
sdi_rx_vpid_byte1_b_# 9 Output 8*N
sdi_rx_vpid_byte2_b_# 9 Output 8*N
sdi_rx_vpid_byte3_b_# 9 Output 8*N
sdi_rx_vpid_byte4_b_# 9 Output 8*N
sdi_rx_vpid_checksum_error_b_# 9 Output N
sdi_rx_vpid_valid_b_# 9 Output N
sdi_tx_reset_# 9 Input 1 SDI TX IP reset.
tx_vid_data_# 9 Input 20*N Transmitter parallel video data input
tx_vid_datavalid_# 9 Input 1 Data valid for the transmitter parallel data. The timing (H:High, L:Low) must be as follows and synchronous to tx_pclk clock domain:
  • SD-SDI: 1H 4L 1H 5L
  • HD-SDI: 1H 1L (for triple/multirate)
  • H (for single rate)
  • 3G/6G/12G-SDI: H
tx_vid_std_# 9 Input 3 Indicates the desired transmit video standard.
  • 3’b000: SD-SDI
  • 3’b001: HD-SDI
  • 3’b011: 3G-SDI Level A 10-bit Multiplex
  • 3’b010: 3G-SDI Level B 10-bit Multiplex
  • 3’b101: 6G-SDI 10-bit Multiplex Type 1
  • 3’b100: 6G-SDI 10-bit Multiplex Type 2
  • 3’b111: 12G-SDI 10-bit Multiplex Type 1
  • 3’b110: 12G-SDI 10-bit Multiplex Type 2
tx_vid_trs_# 9 Input 1 Transmitter TRS input. For use in line number, CRC or payload ID insertion. Assert on first word of both EAV and SAV TRSs.
sdi_tx_enable_crc_# 9 Input 1 Enable CRC insertion for all SDI video standards except SD-SDI.
sdi_tx_enable_ln_# 9 Input 1 Enable Line Number insertion for all SDI video standards except SD-SDI.
sdi_tx_ln_# 9 Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1.
sdi_tx_ln_b_# 9 Input 11*N Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit Multiplex Type 2.
sdi_tx_vpid_overwrite_# 9 Input 1 Enable this signal to overwrite the existing payload ID embedded in the data stream.
sdi_tx_line_f0_# 9 Input 11*N Indicates the line number to be inserted with Payload ID.
sdi_tx_line_f1_# 9 Input 11*N
sdi_tx_vpid_byte1_# 9 Input 8*N Payload ID byte to be inserted in the payload ID field.
di_tx_vpid_byte2_# 9 Input 8*N
sdi_tx_vpid_byte3_# 9 Input 8*N
sdi_tx_vpid_byte4_# 9 Input 8*N
sdi_tx_vpid_byte1_b_# 9 Input 8*N
sdi_tx_vpid_byte2_b_# 9 Input 8*N
sdi_tx_vpid_byte3_b_# 9 Input 8*N
sdi_tx_vpid_byte4_b_# 9 Input 8*N
sdi_tx_datavalid_# 9 Output 1 Data valid signal generated from SDI TX IP and has the following timing synchronous to tx_vid_clkout:
  • SD-SDI: 1H 4L 1H 5L
  • HD-SDI: 1H 1L (for triple/multirate)
  • H (for single rate)
  • 3G/6G/12G-SDI: H
Table 27.  Dynamic Reconfiguration Top Signals Video Standard is triple rate or multirate.
Signal Name 10 Direction Width 7 Description
i_rx_cdr_refclk_p_# Input 1 RX transceiver reference clock.
i_rx_coreclkin_# Input 1 SDI RX IP clock. This clock must be a free-running clock and range between 100 and 156.25 MHz.
i_rx_reset_# Input 1 RX PHY reset signal.
i_rx_serial_data_p_ch0 Input 1 RX transceiver serial data.
i_rx_serial_data_n_ch0 Input 1 Differential pair of rx_serial_data.
o_rx_clkout_# Output 1 System PLL clkout divide by 2.
o_rx_clkout2_# Output 1 RX transceiver recovered parallel clock for video data.
o_rx_is_lockedtodata_# Output 1 Indicates RX is locked to data
o_rx_is_lockedtoref_# Output 1 Indicates RX is locked to reference clock.
o_rx_parallel_data_# Output 80 RX parallel data.
o_rx_ready_# Output 1 Indicates that RX transceiver is out of reset and ready for data transfer.
o_rx_reset_ack_# Output 1 Indicates that RX transceiver is reset.
i_tx_cadence_fast_clk_# Input 1 Fast clock input for tx_cadence generator. This clock should be the system clock used (or (system clock)/2 when IP Interface is double width).
i_tx_cadence_slow_clk_# Input 1 Slow clock input for tx_cadence generator. This clock should be the PMA word or bond clock (or (PMA word or bond clock)/2 when IP Interface is double width).
i_tx_coreclkin_# Input 1 TX parallel clock input.
i_tx_parallel_data_# Input 80 TX parallel data.
i_tx_pll_refclk_p_# Input 1 SDI TX IP parallel clock. This clock must be driven by one of the TX transceivers recovered parallel clocks.
i_tx_reset_# Input 1 TX PHY reset signal
o_tx_cadence_# Output 1 This signal indicates the rate at which tx_datavalid pin needs to be asserted or deasserted when system is running at a higher clock rate then PMA word or bond clock.
o_tx_clkout_# Output 1 System PLL clkout divide by 2.
o_tx_clkout2_# Output 1 TX transceiver recovered parallel clock for video data.
o_tx_pll_locked_# Output 1 TX PLL lock status.
o_tx_ready_# Output 1 Indicates that TX transceiver is out of reset and ready for data transfer.
o_tx_reset_ack_# Output 1 Indicates that TX transceiver is reset.
o_tx_serial_data_p_ch0 Output 1 TX transceiver serial data.
o_tx_serial_data_n_ch0 Output 1 Differential pair of tx_serial_data.
i_pma_cu_clk_bank0 Input 1 PMA control unit clock output, 1 per quad of a shoreline.
i_rs_grant_ch0 Input 1 Grant from SRC shoreline sequencer to SRC lane that allows SRC lane to drive or toggle a reset
i_system_pll_clk Input 1 System PLL output clock. This port must be connected to the system PLL output port from GTS System PLL Clocks FPGA IP.
i_system_pll_lock Input 1 Lock signal of System PLL.
o_rs_request_ch0 Output 1 Request from SRC Lane to the SRC Shoreline Sequencer when it wants to toggle a reset.
rx_vid_data_# 9 Output 20*N

Receiver parallel video data out.
rx_vid_datavalid_#9 Output 1

Data valid signal generated from SDI RX IP and has the following timing synchronous to rx_vid_clkout:

SD-SDI: 1H 4L 1H 5L

HD/3G/6G/12G-SDI: H
rx_vid_std_# 9 Output 3

Received video standard.

3’b000: SD-SDI

3’b001: HD-SDI

3’b011: 3G-SDI Level A 10-bit Multiplex

3’b010: 3G-SDI Level B 10-bit Multiplex

3’b101: 6G-SDI 10-bit Multiplex Type 1

3’b100: 6G-SDI 10-bit Multiplex Type 2

3’b111: 12G-SDI 10-bit Multiplex Type 1

3’b110: 12G-SDI 10-bit Multiplex Type 2
rx_vid_locked_# 9 Output 1

Frame locked indicating the IP spots multiple frames with same timing.
rx_vid_hsync_# 9 Output N

Horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
rx_vid_vsync_# 9 Output N

Vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
rx_vid_f_# 9 Output N

Field bit timing signal. This signal indicates which video field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.

rx_vid_trs_# 9 Output N

Receiver output signal that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.
sdi_rx_rst_proto_out_# 9 Output 1

Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.

sdi_rx_align_locked_# 9 Output 1

Alignment locked indicating a TRS has been spotted and word alignment performed.
sdi_rx_trs_locked_# 9 Output N

TRS locked indicating the IP spots six consecutive TRS with same timing.
sdi_rx_clkout_is_ntsc_paln_# 9 Output 1

Indicates that the receiver is receiving video rate at integer or fractional frame rate.

0 – Integer frame rate

1 – Fractional frame rate
sdi_rx_format_# 9 Output 4

Received video transport format.
sdi_rx_ap_# 9 Output N

Active picture interval timing signal. This signal is asserted when the active picture interval is active.
sdi_rx_eav_# 9 Output N

Receiver output signal that indicates current TRS is EAV. This signal is asserted at the fourth word of TRS, which is the XYZ word.

sdi_rx_ln_# 9 Output 11*N

Received line number output from protocol.
sdi_rx_ln_b_# 9 Output 11*N
sdi_rx_crc_error_c_# 9 Output N

CRC error status signal from protocol.
sdi_rx_crc_error_y_# 9 Output N
sdi_rx_crc_error_c_b_# 9 Output N
sdi_rx_crc_error_y_b_# 9 Output N
sdi_rx_line_f0_# 9 Output 11*N

Payload ID status signal from protocol.
sdi_rx_line_f1_# 9 Output 11*N
sdi_rx_vpid_byte1_# 9 Output 8*N
sdi_rx_vpid_byte2_# 9 Output 8*N
sdi_rx_vpid_byte3_# 9 Output 8*N
sdi_rx_vpid_byte4_# 9 Output 8*N
sdi_rx_vpid_checksum_error_#9 Output N
sdi_rx_vpid_valid_# 9 Output N
sdi_rx_vpid_byte1_b_# 9 Output 8*N
sdi_rx_vpid_byte2_b_# 9 Output 8*N
sdi_rx_vpid_byte3_b_# 9 Output 8*N
sdi_rx_vpid_byte4_b_# 9 Output 8*N
sdi_rx_vpid_checksum_error_b_# 9 Output N
sdi_rx_vpid_valid_b_# 9 Output N
sdi_tx_reset_# 9 Input 1

SDI TX IP reset.
tx_vid_data_# 9 Input 20*N

Transmitter parallel video data input
tx_vid_datavalid_# 9 Input 1

Data valid for the transmitter parallel data. The timing (H:High, L:Low) must be as follows and synchronous to tx_pclk clock domain:

SD-SDI: 1H 4L 1H 5L

HD-SDI: 1H 1L (for triple/multi rate)

H (for single rate)

3G/6G/12G-SDI: H
tx_vid_std_# 9 Input 3

Indicates the desired transmit video standard.

3’b000: SD-SDI

3’b001: HD-SDI

3’b011: 3G-SDI Level A 10-bit Multiplex

3’b010: 3G-SDI Level B 10-bit Multiplex

3’b101: 6G-SDI 10-bit Multiplex Type 1

3’b100: 6G-SDI 10-bit Multiplex Type 2

3’b111: 12G-SDI 10-bit Multiplex Type 1

3’b110: 12G-SDI 10-bit Multiplex Type 2
tx_vid_trs_# 9 Input 1

Transmitter TRS input. For use in line number, CRC or payload ID insertion. Assert on first word of both EAV and SAV TRSs.

sdi_tx_enable_crc_# Input 1

Enable CRC insertion for all SDI video standards except SD-SDI.
sdi_tx_enable_ln_# Input 1

Enable Line Number insertion for all SDI video standards except SD-SDI.
sdi_tx_ln_# 9 Input 11*N

Line number to be inserted in the data stream when sdi_tx_enable_ln = 1.
sdi_tx_ln_b_# 9 Input 11*N

Line number to be inserted in the data stream when sdi_tx_enable_ln = 1. For 3G level B and 6G/12G 10-bit Multiplex Type 2.
sdi_tx_vpid_overwrite_# 9 Input 1

Enable this signal to overwrite the existing payload ID embedded in the data stream.
sdi_tx_line_f0_# 9 Input 11*N

Indicates the line number to be inserted with Payload ID.
sdi_tx_line_f1_# 9 Input 11*N
sdi_tx_vpid_byte1_# 9 Input 8*N

Payload ID byte to be inserted in the payload ID field.
sdi_tx_vpid_byte2_# 9 Input 8*N
sdi_tx_vpid_byte3_# 9 Input 8*N
sdi_tx_vpid_byte4_# 9 Input 8*N
sdi_tx_vpid_byte1_b_# 9 Input 8*N
sdi_tx_vpid_byte2_b_# 9 Input 8*N
sdi_tx_vpid_byte3_b_# 9 Input 8*N
sdi_tx_vpid_byte4_b_# 9 Input 8*N
sdi_tx_datavalid_# 9 Output 1

Data valid signal generated from SDI TX IP. It has the following timing synchronous to tx_vid_clkout:

SD-SDI: 1H 4L 1H 5L

HD-SDI: 1H 1L (for triple/multi rate)

H (for single rate)

3G/6G/12G-SDI: H
gxb_ltd_# Output 1 Set to locktodata control for transceiver.
gxb_rx_set_locktoref_# Output 1 Set to locktoref control for transceiver.
dr_in_progress_# Input 1 Overall dynamic reconfiguration switching status
cdr_reconfig_busy_# Output 1 RX CDR reconfiguration status
dr_rx_avmm_address_# Output 7 Reconfiguration Avalon Memroy-Mapped interfaces to dynamic reconfiguration IP.
dr_rx_avmm_read_# Output 1
dr_rx_avmm_readdata_# Input 32
dr_rx_avmm_readdata_valid_# Input 1
dr_rx_avmm_waitrequest_# Input 1
dr_rx_avmm_write_# Output 1
dr_rx_avmm_writedata_# Output 32
i_dr_lavmm_addr_ch0 Input 21 Reconfiguration interface signals from reconfigure management block to dynamic reconfiguration top.
i_dr_lavmm_be_ch0 Input 4
i_dr_lavmm_clk_ch0 Input 1
i_dr_lavmm_read_ch0 Input 1
i_dr_lavmm_rstn_ch0 Input 1
i_dr_lavmm_wdata_ch0 Input 32
i_dr_lavmm_write_ch0 Input 1
o_dr_lavmm_rdata_ch0 Output 32
o_dr_lavmm_rdata_valid_ch0 Output 1
o_dr_lavmm_waitreq_ch0 Output 1
one_hot_sel Input 4 Dynamic reconfigurationmux selector interface
rx_sdi_reconfig_done_# Output 1 Indicates back to the RX that the dynamic reconfiguration has finished.
rx_rcfg_mgmt_clk_# Input 1 RX reconfiguration clock signal.
rx_rcfg_mgmt_reset_# Input 1 RX reconfiguration reset signal.
gxb_rx_reconfig_xcvr_clk_# Input 1 Avalon Memory-Mapped interfaces to RX Direct PHY IP.
gxb_rx_reconfig_xcvr_reset_# Input 1
gxb_rx_reconfig_xcvr_avmm_address_# Input 18
gxb_rx_reconfig_xcvr_avmm_byteenable_# Input 4
gxb_rx_reconfig_xcvr_avmm_read_# Input 1
gxb_rx_reconfig_xcvr_avmm_readdata_# Output 32
gxb_rx_reconfig_xcvr_avmm_readdatavalid_# Input 1
gxb_rx_reconfig_xcvr_avmm_waitrequest_# Output 1
gxb_rx_reconfig_xcvr_avmm_write_# Input 1
gxb_rx_reconfig_xcvr_avmm_writedata_# Output 32
gxb_tx_reconfig_xcvr_clk_# Input 1 Reconfiguration interface signals to Direct PHY IP’s Avalon Memory-Mapped interface for PLL’s fractional counter reconfiguration.
gxb_tx_reconfig_xcvr_reset_# Input 1
gxb_tx_reconfig_xcvr_avmm_write_# Input 1
gxb_tx_reconfig_xcvr_avmm_read_# Input 1
gxb_tx_reconfig_xcvr_avmm_writedata_# Input 32
gxb_tx_reconfig_xcvr_avmm_address_# Input 18
gxb_tx_reconfig_xcvr_avmm_byteenable_# Input 4
gxb_tx_reconfig_xcvr_avmm_readdata_# Output 32
gxb_tx_reconfig_xcvr_avmm_readdatavalid_# Output 1
gxb_tx_reconfig_xcvr_avmm_waitrequest_# Output 1
Table 28.  Dynamic Reconfiguration Control Signals
Signal Name Direction Width Description
i_csr_clk Input 1 Reconfiguration clock.
i_cpu_clk Input 1 CPU clock
i_rst_n Input 1 Reset signal. This reset should be sharing the same reset as dynamic reconfiguration IP.
o_profile_id Output 15 Current Profile ID
o_in_progress Output 1 Overall dynamic reconfiguration switching status
o_err_status Output 1 Overall dynamic reconfiguration SIP and firmware error status out
o_fast_sim_clk_sel Output 1 Simulation speed up: i_cpu_clk speed can be increased when o_fast_sim_clk_sel is asserted
i_host_avmm_write Input 1 Reconfiguration Avalon Memory-Mapped interfaces from SDI dynamic reconfiguration management.
i_host_avmm_read Input 1
i_host_avmm_address Input 7
i_host_avmm_writedata Input 32
o_host_avmm_readdata Output 32
o_host_avmm_waitrequest Output 1
o_host_avmm_readdatavalid Output 1
o_one_hot_sel Output 4 Dynamic reconfiguration mux selector interface
o_src_pause_request Output 1 DR SRC Interface
i_src_pause_grant Input 1
o_ch0_lavmm_rstn Output 1 Reconfiguration Avalon Memory-Mapped interfaces to DR top.
o_ch0_lavmm_write Output 1
o_ch0_lavmm_read Output 1
o_ch0_lavmm_addr Output 18
o_ch0_lavmm_wdata Output 32
i_ch0_lavmm_rdata Input 32
i_ch0_lavmm_rdata_valid Input 1
i_ch0_lavmm_waitreq Input 1
dr_new_cfg_applied Input 1 Indicates that the reconfiguration is performed from the dynamic reconfiguration IP.
dr_new_cfg_applied_ack Output 1 Acknowledge signal to the dynamic reconfiguration IP on the reconfiguration done
Table 29.  en_refclk_buffer Module Signals
Signal Name Direction Width Description
clk Input 1 Reconfiguration clock.
reset Input 1 Reset signal. This reset should share the same reset as dynamic reconfiguration IP.
pdp_avmm_waitrequest Input 1 Reconfiguration interface signals to Direct PHY IP’s Avalon Memory-Mapped interface for CLK RX refclk buffer re-enable.
pdp_avmm_readdata Input 32
pdp_byte_enable Output 4
pdp_avmm_write Output 1
pdp_avmm_read Output 1
pdp_avmm_readdatavalid Input 1
pdp_avmm_address Output 20
pdp_avmm_writedata Output 32
Table 30.  Sys Reset Module Signals
Signal Name Direction Width Description
clk Input 1 Clock signal to reset delay module.
async_rstn Input 1 Global reset.
ninit_done_sync Output 1 Reset signal. Indicates device is ready.
out_reset Output 1 Reset signal. Indicates user reset and device has not finished its initialization stage after a programmable delay which is determined by CNTR_BITS parameter.
Note: CNTR_BITS parameter determines the bit width of the delay counter. Default value is set to 16.
Related Information
5 N = 4 for multirate, otherwise N = 1.
6 This parameter is only used in parallel loopback without external VCXO design.
7 N=4 for multirate, otherwise N=1.
8 # = Your dual simplex instance name when Enable Dual Simplex Generation is.on
9 This signal is not available when SDI_II wrapper = BASE only.
10 # = Your dynamic reconfiguration top instance name
Level Two Title