GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 5/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

2.3. Functional Description

Figure 13. Parallel Loopback with Simplex IP SDI_II wrapper is BASE only, Enable Dual Simplex Generation is off

For the parallel loopback design, the transceiver is outside of GTS SDI II IP. The transceiver is instantiated at the TX and RX top-level module. For this design, you can change the transceiver settings based on your needs. PMA Direct PHY TX and RX is separated into simplex IP.

This variant is for designs with:
  • Nextera daughter card with separate channel for TX and RX.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 14. Serial Loopback with Simplex IP SDI_II wrapper is BASE only, Enable Dual Simplex Generation is on)

For the serial loopback design, the transceiver is outside of GTS SDI II IP. The transceiver is instantiated at the dual simplex groups module. For this design, you can change the transceiver settings based on your needs. PMA Direct PHY TX and RX is separated into simplex IP.

This variant is for designs with:
  • FMC loopback card.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 15. Parallel Loopback with Simplex IP (SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is off)
Figure 16. Parallel Loopback with Simplex IP and Dynamic Reconfiguration (SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is off)

For the parallel loopback design, the transceiver is inside of GTS SDI II IP. The transceiver is instantiated at the SDI TX and RX module (IP wrapper). GTS SDI II IP (TX and RX) is separated into simplex IP.

This variant is for designs with:
  • Nextera daughter card with separate channel for TX and RX.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 17. Parallel Loopback with Simplex Mode IP (SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is on)

For the parallel loopback design, the transceiver is inside the dual simplex groups. The transceiver is instantiated at the dual simplex groups module. SDI II IP (TX and RX) is wrapped in the dual simplex group. Both RX and TX transceivers are placed at the same channel.

This variant is for designs with:
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 18. Serial Loopback with Simplex IP SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is on)
Figure 19. Serial Loopback with Simplex IP and Dynamic Reconfiguration SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is on)

For the serial loopback design, the transceiver is inside the dual simplex groups. The transceiver is instantiated at the dynamic reconfiguration top block. SDI II IP (TX and RX) is wrapped in the dynamic reconfiguration top. Both RX and TX transceivers are placed at the same channel.

This variant is for designs with:
  • FMC loopback card.
  • Custom development kit.
    Note: You need to set the pin assignment with the design generated using the custom development kit.
Figure 20. Serial Loopback with Simplex IP and Dynamic Reconfiguration SDI_II wrapper is Both BASE and PHY, Enable Dual Simplex Generation is off)

Section Content
Design Components
Clocking Scheme

Level Two Title