External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 4/03/2023

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Document Table of Contents PLL

When using PLL for external memory interfaces, you must consider the following guidelines:
  • For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. Intel Agilex® 7 M-Series devices support only differential I/O standard on dedicated PLL clock input pin for EMIF IP.
  • Intel® recommends using the fastest possible PLL reference clock frequency available in the drop-down list in the EMIF IP Platform Designer, because doing so provides the best jitter performance.