External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 4/03/2023

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Document Table of Contents DDR4 Address and Command and CLK Lane

Address and command and control signals in a bank cannot be swapped.

Pin mapping must adhere to the requirements defined in the table in the Address and Command Pin Placement for DDR4 topic.

You cannot swap address and command lanes. You cannot swap among AC1/AC2/AC3/AC4 lanes. The address and command lane placement must adhere to the specific placement defined in the table in the DDR4 Data Width Mapping topic.

The T and C lanes for the CLKt/c cannot be swapped with each other, nor can the T and C lanes for the DQS-T/DQS-N be swapped with each other.