External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 4/03/2023

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4.3.7. mem for EMIF

Interface between FPGA and external memory

Table 45.  Interface: memInterface type: conduit
Port Name Direction Description
mem_ck_t output CK Clock (true)
mem_ck_c output CK Clock (complement)
mem_reset_n output Asynchronous Reset
mem_cs output Chip Select
mem_ca output Command/Address Bus
mem_dq bidir Data (read/write)
mem_wck_t output Write Clock (true)
mem_wck_c output Write Clock (complement)
mem_rdqs_t bidir Read Data Strobe (true)
mem_rdqs_c bidir Read Data Strobe (complement)
mem_dmi bidir Data Mask/Data Inversion

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