Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 8/14/2023

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Document Table of Contents

2.2.1. PLL Features

Table 2.  PLL Features in M-Series Devices—Preliminary
Feature I/O Bank I/O PLL 2 Fabric-Feeding I/O PLL2
Integer PLL Yes Yes
Number of C output counter 4 7
M counter divide factor range 4 to 320 4 to 320
N counter divide factor range 1 to 110 1 to 110
C counter divide factor range 1 to 510 1 to 510
Dedicated external clock outputs 3 Yes
Dedicated clock input pins4 5 Yes Yes
External feedback input pin Yes
Source synchronous compensation 6 0 Yes Yes
Direct compensation Yes Yes
Normal compensation 7 Yes Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 8 39.0626 ps 39.0626 ps
Programmable duty cycle Yes Yes
Power down mode Yes Yes
Bandwidth setting9
Spread-spectrum input clock tracking 10 Yes Yes
Table 3.  Spread-Spectrum Input Clocking Supported Profile
Spread-Spectrum Clocking Parameter Setting
Modulation frequency 200 kHz
Center or down spread Down spread
Frequency deviation ±1%
Modulation profile Triangle
2 I/O PLL Type is determined by the Intel Quartus Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor.
3 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL. I/O PLL only supports True Differential Signaling I/O Standard for dedicated external clock outputs.
4 I/O PLL only supports True Differential Signaling I/O Standard for dedicated clock input pins.
5 For Fabric-Feeding I/O PLL located at the UIBSS, the dedicated clock input pins only support 1.2V True Differential Signaling I/O Standard.
6 Non-dedicated feedback path option is available for this compensation mode.
7 Non-dedicated feedback path option is also available for normal compensation
8 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the M-Series devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
9 Bandwidth setting is selected by the Intel Quartus Prime software automatically depending on the M counter value.
10 Provided that input clock jitter is within the input jitter tolerance specifications. Intel recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.