18.104.22.168. Output Clock Duty Cycle Correction
M-Series FPGAs have duty cycle correction capability for the following output clocks:
- 3.2 GHz clock for DDR5/LPDDR5
- PHY clock
- PHY clock tree synchronous reset
- Feedback from PHY clock tree
Perform duty cycle correction after power up and PLL reset. Before performing the duty cycle correction, you must successfully complete power up calibration and static phase error calibration. The PLL asserts the lock signal only when the output clock duty cycle correction is complete.