Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 8/14/2023

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Document Table of Contents

1.2. PLLs Overview

Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Intel Agilex® 7 FPGA M-Series devices contain the following I/O PLLs for core applications. The I/O PLLs can only function as integer PLLs.

  • Fabric-feeding I/O PLLs—seven C counter outputs available. For fabric-feeding I/O PLL located in I/O banks, PLL cascading and reconfiguration are supported. However, cascading, dynamic phase shift, and reconfiguration are not supported for fabric-feeding I/O PLL located in the UIB Subsystem (UIB SS).
  • I/O bank I/O PLLs—four C counter outputs available and support PLL cascading.

The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. In M-Series devices, I/O PLL also resides in the UIBSS. Each I/O bank contains two I/O bank I/O PLLs and one fabric-feeding I/O PLL whereas each UIBSS contains two fabric-feeding I/O PLLs.