Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 8/14/2023
Public

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2.2.4. PLL Architecture

Figure 10. I/O Bank I/O PLL High-Level Block Diagram for M-Series Devices
Figure 11. Fabric-Feeding I/O PLL High-Level Block Diagram for M-Series Devices
Note:
  • The dedicated clock inputs can feed only one PLL via the dedicated clock path. To feed the second PLL, the clock must be routed onto a global clock network.
  • If a global reference clock source is required, this clock must be promoted using the Assignment Editor to promote the PLL refclk to a global signal.
  • Cascade Output to Adjacent I/O PLL is not applicable to fabric-feeding I/O PLLs located in UIBSS as they do not support any type of cascading.