126.96.36.199. Source Synchronous Compensation Mode
If the data and clock signals arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Only one output clock can be compensated in source synchronous compensation mode.
Intel recommends source synchronous mode for source synchronous data transfers.
The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:
- Data pin to the IOE register input
- Clock input pin to the PLL PFD input
The M-Series PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.
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