Intel Agilex® 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 8/14/2023

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2.2.13. PLL Calibration

I/O PLLs include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. M-Series uses the I/O manager to perform calibration routines.

There are four main types of calibration.

  • Power-up calibration—initiates automatically at device power-up and runs during device configuration.
  • User calibration—if you perform dynamic reconfiguration or change the reference clock frequency of the I/O PLL, you must perform user recalibration. You must enable the required calibration sequence.
  • Static Phase Error Calibration—initiates after power up calibration to reduce phase error between reference clock and feedback clocks.
  • Output Clock Duty Cycle Correction—initiates after power up and static phase error calibration to measure and lower duty cycle error of specific output clocks. Lock signal is asserted after this operation completes.

To successfully complete the calibration process, OSC_CLK_1 clocks and all reference clocks driving the I/O PLLs must be stable and free running at the start of FPGA configuration. If clock switchover is enabled, both reference clocks must be present for calibration. During user mode, when the I/O PLL does not detect a reference clock during configuration, calibration attempts continue periodically. After calibration has completed, the I/O PLL is locked automatically.