4.2. Clock Control IP Core Parameters
|Number of Clock Inputs||1, 2, or 4||
Specify the number of input clock sources for the clock control block. You can specify up to four clock inputs.
Clock multiplexing in M-Series devices is implemented using soft logic in the core.
For more information about the optimal clock multiplexing design, refer to the Clock Multiplexing section in the Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations.
|Clock Enable||On or Off||Turn on this option if you want to gate your clock output with an enable signal. This option disables the option to use clock division.|
|Clock Enable Type||Root Level or Distributed Sector Level||Select the clock gates located in the periphery or the gates located in the sector. For more information about the clock gates, refer to the Clock Gating section.|
|Enable Register Mode||Negative Latch or None||Specify if the enable signal should be latched.|
|Clock Divider||On or Off||Turn on this option if you want to use the clock division block in the periphery.
This option disables the option to use clock enable.
|Clock Divider Output Ports||Divide 1x, Divide 1x and 2x, or Divide 1x, 2x and 4x||Specify the combination of passing your clock through, dividing your clock by 2, or dividing your clock by 4.|
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