188.8.131.52. LVDS Compensation Mode
LVDS compensation mode maintains the same data and clock timing relationship at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:
- Data pin-to-SERDES capture register
- Clock input pin-to-SERDES capture register
The output counter must provide the 180° phase shift.
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