18.104.22.168.3. I/O PLL Clock Gate
You can dynamically gate each output counter of the M-Series I/O PLL. This I/O PLL clock gate provides a useful alternative to the root clock gate. The root clock gate can gate only 1 of 7 output counters.
However, the I/O PLL clock gate is not cycle-specific. When you use the I/O PLL clock gate, expect a delay of several clock cycles between the assertion or deassertion of the clock gate and the corresponding change to the clock signal. The number of delay cycles is non-deterministic because the enable signal must be synchronized into the clock domain of the output clock, ensuring a glitch-free gate.