Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbapend

This Yocto recipe appends to the meta-intel-fpga/recipes-bsp recipe and enables the FPGA to SDRAM bridge, if it is required for the device target. This bridge is not required for Intel® Arria® 10 designs.

On devices that require the bridge, the bridge allows mSGDMA to access the HPS SDRAM. This access exposes the full HPS SDRAM to the FPGA device.