Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Layout Transform Configuration Options

The example layout transform has a range of parameters to adjust to the data width based on the number of input planes being processed.

A maximum of 16 CSR mean and variance values are supported. The Planes per sample field sets this upper threshold.

All output data is in FP16 format which is the expected input format for the Intel® FPGA AI Suite.