Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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6.6. Fabric EMIF Design Component

The design provides a 266MHz DDR4-64Bit Avalon® -based memory controller. This EMIF is used solely by the DLA.

The Intel® FPGA AI Suite IP memory interface is configured to be 512 bits wide. The EMIF interface is setup to complement this configuration.