Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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6.5.2. The hps_0 Platform Designer Layer (hps.qys)

The hps_0 layer contains the HPS, an mSGDMA instance (msgdma_0) for the Intel® FPGA AI Suite runtime, and an mSGDMA instance (msgdma_1) for the streaming generation app (S2M variant only).

The example layout transform is also located here and can be replaced by your version.