Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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Document Table of Contents Build Synchronization of FPGA with Software

For a system to function correctly, the release version of each Intel® FPGA AI Suite component, including the compiler, the runtime, and the Intel® FPGA AI Suite IP, must match.

In addition, the AOT file created by the Intel® FPGA AI Suite dla_compiler command must target the same architecture (.arch) file as the Intel® FPGA AI Suite IP.

When Intel® Quartus® Prime compiles the Intel® FPGA AI Suite IP, it generates a build-hash that is embedded into the IP. The runtime software checks this build-hash during runtime and if the hashes do not match then the application aborts and displays a mismatch error.

The Intel® FPGA AI Suite SoC design example is always built with only one instance of the Intel® FPGA AI Suite IP.