Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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3.3.2. Building the FPGA Bitstreams

The Intel® FPGA AI Suite SoC design example also includes prebuilt demonstration FPGA bitstreams. If you want to use the prebuilt demonstration bitstreams in your SD card image, skip ahead to Installing HPS Disk Image Build Prerequisites.

If you build your own bitstreams and do not have an Intel® FPGA AI Suite IP license, then your bitstream have a limit of 10000 inferences. After 10000 inferences, the unlicensed IP refuses to perform any additional inference. To reset the limit, reprogram the FPGA device.

To build the FPGA bitstreams, run the following commands: \
 -ed 4_A10_S2M \
 -n 1 \
$COREDLA_ROOT/example_architectures/A10_Performance.arch \
 --build \
$COREDLA_WORK/a10_perf_bitstream \
 --output-dir $COREDLA_WORK/a10_perf_bitstream

The bitstreams built by these commands support both the M2M execution model and the S2M execution model.