Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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5.1.1. Intel® Quartus® Prime Build Flow

All Intel® FPGA AI Suite design examples are launched at the command line by running the script.

After the build script is invoked, it generates an Intel® FPGA AI Suite IP from the provided architecture file, creates an Intel® Quartus® Prime build directory, builds the Intel® Quartus® Prime project, and produces a bitstream.

The script has several command-line options to select the SoC design example variants. For details about the build script command options, refer to Build Script Options.

Before launching the script, an architecture file is required. The Intel® FPGA AI Suite example architectures are located in directory $COREDLA_ROOT/example_architectures/.

Typical launch usage is as follows: \
  -ed <variant> \
  -a <arch-file> \
  -n 1 \
  --build-dir <dir> \
The command options are defined as follows:
  • The -ed option selects the SoC design example variant to be built. This option is case sensitive. The Intel® FPGA AI Suite SoC design examples comes as the following variants:
    Table 2.  SoC Design Example Variant

    Variant setting


    4_A10_M2M Builds a memory-to-memory (M2M) design for the Intel® Arria® 10 SX SoC FPGA Development Kit
    4_A10_S2M Builds a streaming-to-memory (S2M) design for the Intel® Arria® 10 SX SoC FPGA Development Kit
  • The -a option selects the architecture file.
  • The -n 1 option is the only legal value for this option when you build the SoC design example.
  • The --build-dir option specifies the Intel® Quartus® Prime build.
  • The --build option directs the script to call Intel® Quartus® Prime and create the bitstreams. The script uses these bitstreams when creating the SD card image.

For a complete list of the build script options, refer to "Build Script Options" in PCIe-based Design Example User Guide .

An example of building the Intel® Arria® 10 S2M variant with the A10_Performance architecture in the folder build_a10_perf is as follows: \
  -ed 4_A10_S2M \
  -a $COREDLA_ROOT/example_architectures//A10_Performance.arch \
  -n 1 \
  --build-dir build_a10_perf \

After the design is built, the output products (.sof or .rbf files) must be combined with the SoC Linux system in order to be used. This is done in one of the steps in the script.

Unlike non-SoC FPGA flows, the .sof file is not downloaded to the board via JTAG.

Do not attempt to download the .sof file over JTAG because downloading the file over JTAG does not result in a working system. Also, if you attempt to reprogram a running Linux system with a new .sof file, the Linux system crashes and the reprogramming results in an unpredictable outcome.

The FPGA device is programmed by booting the Linux system on the SoC via the SD card. For details about combining the build .sof file with the SD card image to create a functional solution, refer to Building the Bootable SD Card Image (.wic).