Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 9/06/2023

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6.4. Top Level

After the Intel® Quartus® Prime project has finished executing, the design should look similar to the following image in the Intel® Quartus® Prime Project Navigator:
Figure 10. SoC Design Example Hierarchy

The top-level Verilog file and HPS configuration is derived directly from the GSRD designs located at For more information about the Intel® Arria® 10 SoC GSRD, refer to the following URL:

The GSRD designs have been modified to include the Intel® FPGA AI Suite IP. All unnecessary logic has been removed, which provides a concise design example.

The main Intel® FPGA AI Suite SoC design example is contained within a single Platform Designer system, called system. Double-click this node in the Intel® Quartus® Prime Project Navigator to launch Platform Designer.