8.1.1. Stream Controller Communication Protocol
The Intel® FPGA AI Suite OpenVINO™ plugin running on the HPS system includes a coredla-device component which in turn has a stream controller interface if the "external streaming" flag is enabled by the inference application. This stream controller interface manages the communications from the HPS end to the stream controller microcode module running on the Nios® V microcontroller.
Messages are sent between the HPS and the Nios® V microcontroller using the mailbox RAM which is shared between the two. In the HPS, this RAM is at physical address 0xff210000, and in the Nios® V microcontroller, it is at address 0x40000. The RAM is 4K bytes. The lower 2K is used to send messages from the HPS to the Nios® V microcontroller, and the upper 2K is used to send messages from the Nios® V microcontroller to the HPS.
Message flow is always initiated from the HPS end, and the Nios® V microcontroller always responds with a message. Therefore, after sending any message the HPS end waits until it receives a reply message. This can contain payload data (for example, status information) or just a "no operation" message with no payload.
Each message has a 3 x uint32_t header, which consists of a messageReadyMagicNumber field, a messageType field, and a sequenceID field. This header is followed by a payload, the size of which depends on the messageType. The messageReadyMagicNumber field is set to the value of 0x55225522 when the message is ready to be received
When a message is to be sent, all of the buffer apart from the messageReadyMagicNumber is first written to the mailbox RAM. The sequenceID increments by 1 with every message sent. Then the messageReadyMagicNumber is written. The sending end then waits for the value of messageReadyMagicNumber to change to the value of the sequenceID. This is set by the stream controller microcode module and indicates that the message has been received and processed by the receiving end.