Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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Document Table of Contents

4.6.1. Using Interface Planner

The following steps describe basic operation of the Interface Planner to place NoC design elements:

  1. Ensure that you have already run Analysis & Synthesis, as this document previously describes.
  2. To open the Interface Planner click Tools > Interface Planner.
  3. On the Flow control, click Initialize Interface Planner.
  4. On the Flow control, click View Assignments.
  5. On the Assignments tab, enable or disable specific or groups of project assignments to resolve any conflicts or experiment with different settings. You can filter the list of assignments by assignment name or status.
  6. Click Update Plan on the Flow control to apply the enabled project assignments to your interface plan.
  7. Click Plan Design on the Flow control to interactively place IP cores and other design elements in legal locations in the device periphery. All placeable elements, including NoC elements and periphery elements, appear in the Design Elements list. Refer to Recommended Placement Order for NoC Elements in Interface Planner.
  8. Use any of the following methods to place design elements in the Chip View:
    • Drag NoC elements from the Design Elements list and drop them onto available device resources in the Chip view. You may experience a small delay while dragging as Interface Planner calculates the legal locations.
    • To allow Interface Planner to place an unplaced design element in a legal location, right-click and select Autoplace Selected. You must use Autoplace Selected for all unplaced clocks.
    • Right-click an element in the Design Elements list, and then click Generate Legal Locations to display a list of Legal Locations for the element. Click any legal location in the list to highlight the location in the floorplan. Double-click any location in the list to place the element in the location.
  9. After making all necessary location assignments in Interface Planner, validate the placement by clicking Validate Plan in the Flow pane.
  10. To generate a Tcl script to apply the placement constraints to your project, click Export Constraints in the Flow pane. To automatically run the Tcl script, enable Apply Assignments.
    Figure 48. Export Physical Constraints from Interface Planner to Your Project

  11. To report whether the NoC initiator and target location placement allows your design to meet the bandwidth and transaction size requirements, click the Reports tab, and then double-click Report NoC Performance in the Tasks pane. For report details, refer to NoC Performance Reports in Interface Planner.
    Note: Lower-speed memory protocols and other I/O functions that you implement in the GPIO-B blocks, and that bypass the NoC, can cause conflicts that prevent the use of certain initiator locations. Therefore, before assigning any initiator locations, place HBM2e and external memory controllers, as well as any fixed-location lower speed protocols or GPIO.

For more details on placing NoC initiators and targets, refer to the following related topics: