Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.6.3. Fabric NoC Considerations

If you configure the NoC Initiator Intel FPGA IP with an AXI4 read data width of 512 or 576 bits, the IP implements the fabric NoC feature.

When you use this configuration, instead of delivering read data directly to the initiator read port, read data is written to a column of M20K memory blocks below the NoC initiator, as Figure 11. NoC Initiators With and Without Fabric NoC shows.

This configuration is ideal for applications that rely on high sequential read throughput. Usage of the fabric NoC feature for read data reduces pressure on fabric routing resources near the NoC initiator along the edge of the die.

Additionally, if you configure the NoC Initiator Intel FPGA IP with an AXI4 write data width of 512 or 576 bits, you can choose to implement the IP with a separate clock for the 256-bit wide initiator hardware. That clock can run as fast as 660 MHz for -1 speed grades, 630 MHz for -2 speed grades, and 450 MHz for -3 speed grade devices. With this option you can achieve up to 90% of sustained HBM2e write throughput. These 512-bit interfaces only support transactions that transfer multiples of 64 bytes, and target addresses that are aligned on 64-byte boundaries.