Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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4.5.3. NoC Connection and Addressing Examples

This section provides examples of NoC connections and addressing for several configurations. Each configuration includes examples for the Platform Designer connection flow and for the NoC Assignment Editor flow, as NoC Design Flow Options describes.

For both connection flows, you specify NoC group, bandwidth, and transaction size assignments in the NoC Assignment Editor, as Using the NoC Assignment Editor describes.

Table 8.  Specifying Connections and Addressing Per Flow
Connection Flow Make Connections In Specify Addressing In
Platform Designer Connection Flow Platform Designer System View tab Platform Designer Address Map tab
NoC Assignment Editor Connection Flow NoC Assignment Editor Connection tab NoC Assignment Editor Attributes tab
Note: Connections and addresses that you make in the Platform Designer connection flow also appear in the NoC Assignment Editor, but the connections appear as read-only.