Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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Document Table of Contents Step 4: Validate Logical NoC Assignments and Generate Simulation File

After creating all necessary group, connection, and attribute assignments in the NoC Assignment Editor, follow these steps to validate the logical NoC assignments and generate the simulation file for the NoC:

  1. Click the Validate button on the NoC Assignment Editor. Validation performs design rule checks, such as ensuring that there is exactly one PLL in each NoC group, and that each NoC initiator has at least one connection. Additionally, validation ensures there are no address space overlaps in your base address assignments. Any design rule check violations display in the lower portion of the NoC Assignment Editor.
  2. After resolving any errors or warnings, click the Save button to write the assignments to the project .qsf. The registration include file for simulation includes information from the NoC logical assignments.
  3. If your design uses the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, re-run Analysis & Elaboration to update the registration include file after you make any change to these assignments using either the NoC Assignment Editor or directly in the .qsf.
  4. After completing logical assignments, run Analysis & Synthesis to prepare the design to make physical assignments using the Interface Planner.

For more details on the registration include file and the NoC simulation flow, refer to Simulating NoC Designs.