Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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4.5.1. Creating NoC Assignments for Compilation

After instantiating NoC-related IP in your design, connecting initiators to AXI4 managers, and connecting other NoC IP to external ports, you next run Intel® Quartus® Prime Analysis & Elaboration on your design. Analysis & Elaboration reads your design, discovers the hard memory NoC-related IP in your design, and determines the location of the IP in the design hierarchy. Once Analysis & Elaboration is complete, open the NoC Assignment Editor to enter the NoC logical assignments.

If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, the connection and address map assignments that you create in Platform Designer automatically import into the NoC Assignment Editor as read-only assignments. If you need to change these connection and address map assignments, return to Platform Designer and make the necessary changes there. You specify the remaining NoC group and read and write bandwidth and transaction size requirements in the NoC Assignment Editor.

If your design uses the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, you must re-run Analysis & Elaboration after completing the logical assignments. This step allows you to generate the simulation registration file that communicates connection and address mapping to your simulation environment. If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, this simulation registration file generates when you generate HDL for your Platform Designer system. For simulation flow details, refer to Simulating NoC Designs.

To proceed to compilation, run Analysis & Synthesis to prepare your design for physical assignments. You can optionally use the Intel® Quartus® Prime Interface Planner to assign locations for hard memory NoC initiator, target, PLL, and SSM blocks, and make assignments for other I/O-related IP, as Step 5: Make Physical Assignments Using Interface Planner describes.