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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
4.4.1. General NoC IP Connectivity Guidelines
4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
4.4.4. Connectivity Guidelines: NoC Clock Control
4.4.5. Connectivity Guidelines: NoC Initiators for HPS
4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator
4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator
4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator
4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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4.4.6. Connectivity Guidelines: NoC Targets for HPS
The External Memory Interfaces for HPS Intel FPGA IP contains the NoC target bridges for HPS. Make any clocking, reset, calibration, or external I/O connections for this IP in accordance with the user guide guidelines for this IP.
- If you are using the Platform Designer connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer. Connect the HPS AXI4 NoC subordinate interface on the External Memory Interfaces for HPS Intel FPGA IP only to the AXI4 NoC manager interfaces on the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP. Do not connect the target bridges in the HPS EMIF IP to any fabric-facing NoC Initiator bridge. After connecting the HPS AXI4 NoC manager and HPS AXI4 NoC subordinate interfaces, click the Address Map tab, to specify the base address for each connection. If an HPS AXI4 NoC manager interface connects to multiple HPS AXI4 NoC subordinate interfaces, ensure each connection has a unique starting address. You can click the Assign Base Addresses button to allow Platform Designer to assign addresses automatically.
- If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer and leave the HPS AXI4 NoC subordinate interface unconnected. After running Intel® Quartus® Prime Analysis & Elaboration, you can use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation. Note that HPS designs only support design entry using Platform Designer. HPS designs do not support direct RTL instantiation.
For details on HPS EMIF IP, refer to refer to the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide.
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