Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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Document Table of Contents Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator

Example 1 represents a single AXI4 manager in the fabric communicating to a single external memory interface.

Example 1 contains one instance of the External Memory Interfaces (EMIF) IP and two instances of the NoC Initiator Intel FPGA IP:

  • The first initiator has a single AXI4 interface, and connects to the main AXI4 target interface of the external memory interface.
  • The second initiator has a single AXI4-Lite interface and connects to the sideband AXI4-Lite interface of the external memory interface.

Each initiator interface connects to only one target interface. Each connection uses a base address of 0x0000. Example 1 also contains one instance of the NoC Clock Control Intel FPGA IP, but its AXI4-Lite interface is unconnected.