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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
4.4.1. General NoC IP Connectivity Guidelines
4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
4.4.4. Connectivity Guidelines: NoC Clock Control
4.4.5. Connectivity Guidelines: NoC Initiators for HPS
4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator
4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator
4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator
4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
Example 1 represents a single AXI4 manager in the fabric communicating to a single external memory interface.
Example 1 contains one instance of the External Memory Interfaces (EMIF) IP and two instances of the NoC Initiator Intel FPGA IP:
- The first initiator has a single AXI4 interface, and connects to the main AXI4 target interface of the external memory interface.
- The second initiator has a single AXI4-Lite interface and connects to the sideband AXI4-Lite interface of the external memory interface.
Each initiator interface connects to only one target interface. Each connection uses a base address of 0x0000. Example 1 also contains one instance of the NoC Clock Control Intel FPGA IP, but its AXI4-Lite interface is unconnected.