Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator

Example 3 represents two AXI4 managers in the fabric communicating to a single external memory interface.

Example 3 contains one instance of the External Memory Interfaces (EMIF) IP and three instances of the NoC Initiator Intel FPGA IP:

  • Two of the initiators have a single AXI4 interface, and connect to the main AXI4 target interface of each external memory interface.
  • The third initiator has a single AXI4-Lite initiator interface and connects to the sideband AXI4-Lite interface of the external memory interface.

Both AXI4 initiator interfaces connect to the same target interface. Each AXI4 initiator interface has access to the full memory space, and uses an address of 0x000000000 for the memory. The AXI4-Lite initiator interface uses an address of 0x0000000 for the memory sideband interface.

Example 3 also contains one instance of the NoC Clock Control Intel FPGA IP, but the AXI4-Lite interface is unconnected.