Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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4.5. Making NoC Logical Assignments

The Compiler applies several logical assignments for the NoC during Intel® Quartus® Prime compilation. You can use the NoC Assignment Editor to create and validate these assignments. These logical assignments include the following:

  • Group (required)—assign NoC IP in your design to one of two groups. The Fitter places one group in the hard memory NoC along the top edge of the die, and the other group in the hard memory NoC along the bottom edge of the die.
  • Connection (required)—specify which NoC initiator bridges communicate with which NoC target bridges.
  • Addressing (required)—for each NoC initiator bridge, define the address map for the connected NoC target bridges.
  • Read and write bandwidth and transaction size (recommended)—enter the anticipated read and write bandwidth requirements and transaction sizes for each NoC initiator bridge-to-target bridge connection. The Intel® Quartus® Prime Compiler uses this information to analyze whether there is congestion on the hard memory NoC.