Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 10/12/2023

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Document Table of Contents Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator

Example 4 represents two AXI4 managers in the fabric and two pseudo-channels of high-bandwidth memory in a crossbar configuration.

In this configuration, each AXI4 manager can communicate with each pseudo-channel of the high-bandwidth memory. Example 4 contains one instance of the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP with only one channel or two pseudo-channels.

Example 4 also contains one instance of the NoC Initiator Intel FPGA IP with two AXI4 interfaces and one AXI4-Lite interface.

This configuration implements two NoC initiator bridges, where the first bridge is shared between the first AXI4 interface and the AXI4-Lite interface, and the second bridge is dedicated for the second AXI4 interface, as NoC Initiators for Fabric AXI4 Managers describes.

Both AXI4 interfaces connect to both high-bandwidth memory pseudo-channels in a crossbar configuration. The first AXI4 interface also connects to the high-bandwidth memory sideband interface. Each AXI4 initiator interface uses 0x00000000 as the base address for the first pseudo-channel, and 0x40000000 as the base address for the second pseudo channel. The first AXI4 initiator interface also uses 0x80000000 as the base address for the sideband channel.

The example also contains one instance of the NoC Clock Control Intel FPGA IP, but the AXI4-Lite interface is unconnected.