F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

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2.4.1. Testbench

Figure 6. Block Diagram of the F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench
Table 5.  Testbench Components
Component Description
Device under test (DUT) The 25G Ethernet Intel FPGA IP core.
Ethernet Packet Generator and Packet Monitor
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the simulator console.
F-Tile Reference and System PLL Clocks Intel® FPGA IP Generates transceiver and system PLL reference clocks.