1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.1. Directory Structure
Figure 2. 25G Ethernet Intel FPGA IP Design Example Directory Structure
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only design example is located in <design_example_dir>/compilation_test_design.
- The hardware configuration and test files (the design example in hardware) are located in <design_example_dir>/hardware_test_design.
|eth_ex_25g.qpf||Intel® Quartus® Prime project file.|
|eth_ex_25g.qsf||Intel® Quartus® Prime project settings file.|
|eth_ex_25g.sdc||Synopsys Design Constraints file. You can copy and modify this file for your own 25GbE Intel® FPGA IP core design.|
|eth_ex_25g.v||Top-level Verilog HDL design example file.
Single-channel design uses Verilog file.
|common/||Hardware design example support files.|
|hwtest/main.tcl||Main file for accessing System Console.|