F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

1.2.1. Design Example Parameters

Table 2.  Parameters in the Example Design Tab
Parameter Description
Example Design Available example designs for the IP parameter settings. Only single-channel example design is supported for this IP.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, use device AGIB027R31B1E2VRO as the Target Device for design example generation.

Agilex I-series Transceiver-SoC Dev Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device of AGIB027R31B1E2VRO. If your board revision has a different device grade, you can change the target device.

None: This option excludes the hardware aspects for the design example.