F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

ID 750200
Date 10/14/2022

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2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices

The F-tile 25G Ethernet design example demonstrates an Ethernet solution for Intel® Agilex™ devices using the 25G Ethernet Intel FPGA IP core.

Generate the design example from the Example Design tab of the 25G Ethernet Intel FPGA IP parameter editor. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.