F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
ID
750200
Date
10/14/2022
Public
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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1. Quick Start Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 22.3 |
IP Version 1.0.0 |
The F-tile 25G Ethernet Intel FPGA IP for Intel® Agilex™ devices provides the capability of generating design examples for selected configurations.
Figure 1. Design Example Usage