1.1. Directory Structure
Figure 2. F-Tile 25G Ethernet IP Design Example Directory Structure
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only design example is located in <design_example_dir>/compilation_test_design.
- The hardware configuration and test files (the design example in hardware) are located in <design_example_dir>/hardware_test_design/eth_ex_25g.qpf.
File Names |
Description |
---|---|
eth_ex_25g.qpf | Quartus® Prime project file. |
eth_ex_25g.qsf | Quartus® Prime project settings file. |
eth_ex_25g.sdc | Synopsys Design Constraints file. You can copy and modify this file for your own 25GbE IP core design. |
eth_ex_25g.v | Top-level Verilog HDL design example file. Single-channel design uses Verilog file. |
common/ | Hardware design example support files. |
hwtest/main.tcl | Main file for accessing System Console. |