F-Tile 25G Ethernet IP Design Example User Guide

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ID 750200
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet IP Design Example User Guide

5. Document Revision History for F-Tile 25G Ethernet IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.08.11 25.1 9.0.0
  • Added Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4× F-Tile) option in the Target Development Kit selection step in the Generating the Design Example topic.
  • Added Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4× F-Tile) in the Select Board parameter description in the Parameters in the Example Design Tab table.
  • Added Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (AGIB027R31B1E1VB) in the Hardware and Software Requirements topics in the F-Tile 25G Ethernet Single-Channel and Single-Channel with Dynamic Reconfiguration Design Examples.
2025.01.24 24.3.1 8.0.0
  • Updated the development kit display name to Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile) in the following topics:
    • Generating the Design Example
    • Design Example Parameters
    • Hardware and Software Requirements topics for all design example variants.
2023.11.29 23.2 2.0.0
  • Added a new topic: F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration.
2023.06.26 23.2 2.0.0
  • Updated steps in Simulating the F-Tile 25G Ethernet Intel FPGA Design Example Testbench topic.
  • Updated steps in Test Procedure topic.
  • Updated product family name to "Intel Agilex® 7"
2022.10.14 22.3 1.0.0 Initial release.
Level Two Title